Scientific Researcher for RISC-V System Software Tools and Debugging - 100%, TV-L E13, Postdoc or PhD candidate (m/f/d)

04.04.2025, Wissenschaftliches Personal

The Chair for Computer Architecture and Parallel Systems (CAPS) offers this position as part of the DARE-project funded by the EuroHPC JU bringing together expertise from a wide range of partners in academia and industry, with both application and system expertise. About us CAPS is part of TUM’s department of Computer Engineering, one of the leading CE departments in Europe. We focus on a wide range of aspects of computer architecture – from edge and IoT devices to HPC and cloud sys-tems, from AI accelerators to quantum computing systems – as well as the needed system software needed to extract a maximum of efficiency form the respective architectures. The latter includes work on programming mod-els, operating systems, scheduling, tools, I/O as well as application optimization. This research focuses on the development of a parallel debugging framework tailored for custom RISC-V instruc-tion set extensions. The goal is to enable efficient execution tracing of both standard and extended RISC-V archi-tectures while maintaining compatibility with existing debugging methodologies and tools. The project addresses critical challenges such as minimizing instrumentation overhead and enabling multi-core/multithread debugging (parallel debugging). By integrating with existing tools (GDB) and extending the de-bugging capabilities, this work aims to provide a robust, adaptable solution for homogeneous/heterogeneous RISC-V systems. Required Qualifications: • Above-average MS degree with emphasis in informatics, computer engineering or a related field. • Very good knowledge of computer and system architecture, as well as performance engineering. • Pleasure in taking responsibility, independent and structured way of working, high commitment, communi-cation and team skills as well as very good English skills. Preferred Qualifications: • Strong interest in RISC-V, architecture and High Performance Computing • Experience with low level software and tools Key objectives include: • Extensible Debugging Architecture: Enhancing traditional GDB debugging interfaces to accommodate domain-specific extensions (example in DARE: VEC: 4-way O3 RISC-V VPU, a link to VEC or SDV V0?), and other custom modifications through emulator-integrated programmable hooks. • Dynamic/Hardware-aware Debugging Contexts: Implementing runtime adaptation to varying RISC-V con-figurations, including non-standard register layouts and memory-mapped peripherals (accelerators), ena-bling automatic recognition of customized debugging symbols (example in DARE: AIPU). • Low-Overhead Instrumentation: Optimizing breakpoint handling, instruction tracing, and execution control within emulation environments to minimize performance impact, particularly for multi-threaded and hetero-geneous workloads. • Cross-Tool Validation: Ensuring consistency in register states, exception handling, and execution behavior through validation against existing software tools and hardware implementations. • Scalable Cross-Core Debugging: Developing mechanisms for synchronized state tracking across multi-core/multithread RISC-V architectures, ensuring consistent register states, memory coherence, and excep-tion handling during debugging sessions. Our Offer We offer an interesting, well-equipped workplace at a renowned university and a pleasant working atmosphere in a nice and very international team. There is also a high degree of flexibility and self-responsibility and the opportuni-ty to present scientific papers at international conferences. Work will be conducted in either collaboration with multiple collaborators at German and/or EU partner sites. Application Please send your complete applications (curriculum vitae, copies of certificates, letter of recommendation if avail-able) until 30.04.2025 by e-mail in the form of a single PDF file, to Prof. Dr. Schulz (schulzm@in.tum.de), cc-ing Lisa Francke (lisa.francke@in.tum.de). Applications received after the application deadline may be considered for future application rounds until the position has been filled. TUM aims to increase the proportion of women and minorities in teaching and research. Qualified women and members of minority groups are therefore explicitly encouraged to apply. Disabled applicants will be given prefer-ence if their suitability and qualifications are otherwise essentially equal. Data protection notice When applying for a position at the Technical University of Munich (TUM), you submit personal data. Please refer to our data protection information in accordance with Art. 13 of the General Data Protection Regulation (DSG-VO) go.tum.de/554159 regarding the collection and processing of personal data as part of your application. By submitting your application, you confirm that you have taken note of the TUM data protection information

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About us

CAPS is part of TUM’s department of Computer Engineering, one of the leading CE departments in Europe. We focus on a wide range of aspects of computer architecture – from edge and IoT devices to HPC and cloud sys-tems, from AI accelerators to quantum computing systems – as well as the needed system software needed to extract a maximum of efficiency form the respective architectures. The latter includes work on programming mod-els, operating systems, scheduling, tools, I/O as well as application optimization.

This research focuses on the development of a parallel debugging framework tailored for custom RISC-V instruc-tion set extensions. The goal is to enable efficient execution tracing of both standard and extended RISC-V archi-tectures while maintaining compatibility with existing debugging methodologies and tools.

The project addresses critical challenges such as minimizing instrumentation overhead and enabling multi-core/multithread debugging (parallel debugging). By integrating with existing tools (GDB) and extending the de-bugging capabilities, this work aims to provide a robust, adaptable solution for homogeneous/heterogeneous RISC-V systems.

Required Qualifications:

• Above-average MS degree with emphasis in informatics, computer engineering or a related field.

• Very good knowledge of computer and system architecture, as well as performance engineering.

• Pleasure in taking responsibility, independent and structured way of working, high commitment, communi-cation and team skills as well as very good English skills.

Preferred Qualifications:

• Strong interest in RISC-V, architecture and High Performance Computing • Experience with low level software and tools Key objectives include:

• Extensible Debugging Architecture: Enhancing traditional GDB debugging interfaces to accommodate domain-specific extensions (example in DARE: VEC: 4-way O3 RISC-V VPU, a link to VEC or SDV V0?), and other custom modifications through emulator-integrated programmable hooks.

• Dynamic/Hardware-aware Debugging Contexts: Implementing runtime adaptation to varying RISC-V con-figurations, including non-standard register layouts and memory-mapped peripherals (accelerators), ena-bling automatic recognition of customized debugging symbols (example in DARE: AIPU).

• Low-Overhead Instrumentation: Optimizing breakpoint handling, instruction tracing, and execution control within emulation environments to minimize performance impact, particularly for multi-threaded and hetero-geneous workloads.

• Cross-Tool Validation: Ensuring consistency in register states, exception handling, and execution behavior through validation against existing software tools and hardware implementations.

• Scalable Cross-Core Debugging: Developing mechanisms for synchronized state tracking across multi-core/multithread RISC-V architectures, ensuring consistent register states, memory coherence, and excep-tion handling during debugging sessions.

Our Offer

We offer an interesting, well-equipped workplace at a renowned university and a pleasant working atmosphere in a nice and very international team. There is also a high degree of flexibility and self-responsibility and the opportuni-ty to present scientific papers at international conferences. Work will be conducted in either collaboration with multiple collaborators at German and/or EU partner sites.

Application

Please send your complete applications (curriculum vitae, copies of certificates, letter of recommendation if avail-able) until 30.04.2025 by e-mail in the form of a single PDF file, to Prof. Dr. Schulz (schulzm@in.tum.de), cc-ing Lisa Francke (lisa.francke@in.tum.de). Applications received after the application deadline may be considered for future application rounds until the position has been filled. TUM aims to increase the proportion of women and minorities in teaching and research. Qualified women and members of minority groups are therefore explicitly encouraged to apply. Disabled applicants will be given prefer-ence if their suitability and qualifications are otherwise essentially equal.

Data protection notice

When applying for a position at the Technical University of Munich (TUM), you submit personal data. Please refer to our data protection information in accordance with Art. 13 of the General Data Protection Regulation (DSG-VO) go.tum.de/554159 regarding the collection and processing of personal data as part of your application. By submitting your application, you confirm that you have taken note of the TUM data protection information.

Kontakt: Prof. Dr. Martin Schulz schulm@in.tum.de, cc-ing Prof. Dr. Carsten Trinitis carsten.trinitis@tum.de and Lisa Francke lisa.francke@tum.de

Mehr Information

https://www.ce.cit.tum.de/caps/startseite/