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Sitemap > Bulletin Board > Diplomarbeiten, Bachelor- und Masterarbeiten > Master/Bachelor thesis: Design and schedulability evaluation of locking protocols for memory-centric scheduling
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Master/Bachelor thesis: Design and schedulability evaluation of locking protocols for memory-centric scheduling

27.10.2021, Diplomarbeiten, Bachelor- und Masterarbeiten

The Chair of Cyber-Physical Systems is offering a Master/Bachelor thesis on schedulability analysis for memory-centric multi-core schedulers. The standard multiprocessor real-time locking protocols can be applied to avoid memory contention by allowing only one core to access the main memory at a time. The main objective of the thesis is to revisit the schedulability analysis of the various state-of-the-art protocols and evaluate their performance through simulation.

The memory system is the main performance and energy bottleneck in modern multiprocessors. In the context of real-time systems where tasks operate under strict timing constraints, limiting or completely removing the inter-core memory interference is particularly important. The low- and high-criticality tasks share the memory system, but the memory controller does not distinguish between tasks’ priorities. Consequently, aggressive memory-intensive tasks with low-priorities can increase (even by a factor of twelve) the memory latency of high-priority memory-sensitive tasks executed simultaneously on a different core.

To tackle this problem, a memory-centric scheduler assigns memory transactions of tasks running on different processors to non-overlapping time slots. Each task is divided into the memory phase, where the data required by the task are fetched from the main memory into private cache or scratchpad memory, and the computation phase, where the tasks execute using only the prefetched data without the need to access the shared main memory. The scheduler might use time-division multiplexing (TDM) [1] or inter-processor interrupts (IPI) [2] as the underlying principle to schedule memory phases of tasks running on different cores. In the first approach, each core is statically assigned an individual time slot for its memory phases, and in the second approach, a core requesting memory access sends an interrupt to the other cores, and, depending on the arbitration results, the other cores stop their memory phases, or the requesting core is placed in the waiting queue. The downside is less flexibility, in the case of the TDM approach, and high overheads, in the case of the IPIs. Surprisingly, the common synchronization mechanisms (e.g., spinlock) have been unexplored in the context of memory-centric scheduling and can overcome the disadvantages of the other approaches.

In this thesis, we will revisit the multiprocessor resources access protocols and their application to memory-centric scheduling. The main objective is to adapt the schedulability analysis of different multiprocessor real-time locking protocols for a single resource, that is, memory, and conduct the schedulability performance comparison. The evaluation is to be carried out using a synthetic task set generator [3] and based on the real task characteristics. (Note to the students who completed the Concepts and Software Design for Cyber-Physical Systems: the proposed project is an extension to Priority Inheritance and Ceiling Protocols schedulability analysis for multi-core platforms.)

For further information, please contact:
Dr. Tomasz Kloda

[1] Rohan Tabish, Renato Mancuso, Saud Wasly, Rodolfo Pellizzoni, Marco Caccamo. A real-time scratchpad-centric OS with predictable inter/intra-core communication for multi-core embedded systems. Real-Time Systems, 2019, Vol. 55, No. 4, 01.10.2019, p. 850-888.

[2] Gero Schwäricke, Tomasz Kloda, Giovani Gracioli, Marko Bertogna, Marco Caccamo. Fixed-Priority Memory-Centric Scheduler for COTS-Based Multiprocessors. ECRTS 2020: 1:1-1:24 https://drops.dagstuhl.de/opus/volltexte/2020/12364/pdf/LIPIcs-ECRTS-2020-1.pdf

[3] https://github.com/brandenburg/schedcat

Kontakt: tomasz.kloda@tum.de

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