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Master thesis: Memory-centric scheduler for virtualized multicore real-time systems

27.10.2021, Diplomarbeiten, Bachelor- und Masterarbeiten

The Chair of Cyber-Physical Systems is offering a Master thesis on memory-centric scheduler implementation for multi-core platforms. The main objective of the thesis is to implement a locking mechanism at the hypervisor level to limit concurrent access to the main memory. The solution targets Bao real-time hypervisor.

Virtualization is increasingly used in the domain of safety-critical systems. Hypervisors take advantage of multicore processors by simultaneously running high- and low-criticality applications on a single hardware platform. The underpinning principle is the hardware partitioning that allows the assignment of individual processors and devices to particular operating systems (OS). The software of one OS cannot, therefore, access or manipulate another OS and overwrite the memory allocated to the other OS with faulty data or use another OS processing capacity. Also, the shared resources, like last-level caches or main memory, can be partitioned among different applications. However, spatial partitioning, especially in the case of the memory system, might not be sufficient to guarantee freedom from interference when multiple cores or devices access the memory simultaneously, and, due to the limited parallelism of the memory controller, the memory latency can be increased, even by a factor of twelve as shown by the recent studies (i.e., since memory controller does not distinguish between tasks’ priorities, a task running on one core can be delayed by an aggressive memory-intensive task running on another core).

The aim of this thesis is to implement temporal partitioning for the memory system in the Bao real-time hypervisor [1,2]. We will propose a locking mechanism to ensure that only one high-criticality task can access the main memory at a time without any interference from the low-criticality tasks. Our model assumes segmented-task execution where each task is divided into memory and computation phases. During the memory phase, the data required by the task are fetched from the main memory into the task’s private cache partition, and during the computation phase, the task executes using only the prefetched data without the need to access the shared main memory. The target architecture will be Armv8-A.


For further information, please contact:
Dr. Tomasz Kloda


[1] Martins, José, Adriano Tavares, Marco Solieri, Marko Bertogna and Sandro Pinto. “Bao: A Lightweight Static Partitioning Hypervisor for Modern Multi-Core Embedded Systems.” NG-RES@HiPEAC (2020).
https://drops.dagstuhl.de/opus/volltexte/2020/11779/pdf/OASIcs-NG-RES-2020-3.pdf

[2] https://github.com/bao-project/bao-hypervisor

Kontakt: tomasz.kloda@tum.de

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